The Altera-provided SPI slave component is configurable in several ways:
- Data format: MSB-first or LSB-first
- Data width: 1 to 16 bits
- Clock polarity (CPOL): non-inverted or inverted
- Clock phase (CPHA): leading or trailing edge sample
(The data-related stuff is obvious; see Wikipedia for a decent explanation of CPOL and CPHA.)
I see a way to make my task easier: drop configurable CPOL and CPHA. That sort of configurability in an SPI slave is a useless feature, and I can prove it. First, consider this fact: most existing SPI slaves lack CPHA and CPOL configurability. (Imagine a cheap SPI-equipped ADC chip. If it were configurable, how would you configure it? By tying pins high or low? Too expensive. By init-time communication via secret codes from the SPI master? Well, I'm sure you see the problem with that idea.) Because there are exist non-configurable SPI slaves, SPI masters (like the one in the f20123) must pick up the slack and provide variable CPHA and CPOL. There's no value in making both ends of the link configurable, so I'll drop that bit of needless complexity and choose CPOL=0, CPHA=0 for my new SPI slave.
That's a relief. Fewer features means less complexity, fewer bugs, easier testing. So, what features do I deem useful enough to implement?
- Data width: 1 up to some huge number, why not.
- MSB-first or LSB-first data
- Proper operation if SS_n is tied low (in other words, don't rely on SS_n falling or rising edges). But do resynchronize on inactive SS_n, if it occurs.
- Double-buffered transmit and receive registers
- Avalon-ST source and sink interfaces, or Avalon-MM slave interface with flow control
- Verilog or VHDL implementation, which must be at least barely human-readable
That'll do. Next time: some block diagrams.