Aaron's Sandbox

Time for another distracting tangent. The tb_8 system consists of:

1. a JTAG UART (104 LEs)
2. my little custom byte-pipe (9 LEs)
3. an 8-bit SPI slave (40 LEs)

The first two components are beyond reproach: the JTAG UART because I have no idea how it works, but it works, and my little byte-pipe because it's so cute and tiny.

But the SPI slave; that's another matter. My feeling upon reading the HDL implementation, spi.v, is that its designer was not only criminally incompetent, but also completely disinterested in producing legible code. And maybe 40 LEs is not so much, but I believe I can do better. Also, in the process of doing this reimplementation, I can write a few words on my favorite hardware design methodology, "Europa".

To wrap up, here are the metrics by which I'll judge the existing spi.v versus my new implementation, in priority order:

• Proper function
• HDL readability
• Configurability. I'm thinking I need to support both flavors of clock polarity and clock phase, and also various data widths.
• FPGA resource consumption

There you have it. The challenge is on!