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A Little Chat about Verilog & Europa

Say, what's in my FPGA? Just a sea of configurable wires, registers, and logic. Without a configuration bitstream, the FPGA does nothing (well, it eagerly awaits a bitstream. It does almost nothing.) How do I create that bitstream? Assuming I have some digital logic function in mind, I have only to translate my design intent into one of a handful of gratuitously cryptic hardware-description "languages" and throw it in Quartus' lap. Among my choices are:

  • block diagrams full of little schematic symbols
  • Verilog
  • VHDL
  • an Altera-created hardware description called AHDL

But I eschew all that for a different Altera creation: a collection of perl modules called Europa.

First, the history. Long ago, some clever engineers needed to wire a little soft-core CPU to its UART, onchip memory, PIOs and other peripherals. They could have just banged out a Verilog description of the interconnections and called it a day, but that was too easy. Also, what if someone wanted eleven UARTs? What if they somehow thought VHDL was better? Then what? Clearly, automatic generation of the interconnect bus was indicated, and while we're at it, go ahead and generate the HDL for the UART and PIO as well. What better language in which to write a generator program than Perl? Case closed.

Time for a simple example. Consider the following logic, displayed in a format which still, for me, resonates deeply:


(I hope the notation is clear: the diagram shows a module named simple, which has some inputs, an OR gate, a D-flip-flop, and an output.)

Module simple translates fairly readily to Verilog:

module simple(
  input clk;
  input reset_n;
  input a;
  input b;
  output x;

  wire tmp;
  assign tmp = a | b;
  reg x;

  always @(posedge clk or negedge reset_n)
    if (~reset_n) x <= 1'b0;
    else x <= tmp;


Even in this extremely simple example, you can see Verilog's flaws. The module's inputs and output are listed twice: once in the module port list and again as input and output declarations within the module. A different sort of redundancy exists between a given signal's direction (as input, output or neither - internal) and its role in the described logic (signal with no source, signal with no sink or signal with both source and sink). Here's the Europa equivalent of the above Verilog, which solves those problems:

use europa_all;

my $project = e_project->new({
  do_write_ptf => 0,

my $module = e_module->new({name => "simple"});
    lhs => "tmp",
    rhs => "a | b",
    out => "x",
    in => "tmp",
    enable => "1'b1",


The benefits are clear:

  • redundancy is eliminated
  • Perl is a real programming language, and fun besides
  • Even in this simple example, fewer bytes/keystrokes are required to encode the design
  • I didn't show it here, but VHDL output is available (controlled by an e_project setting)

So there you have it. I can merrily go off and build my SPI slave component in Europa, and generate to the HDL of my choice. Great!

However! I couldn't very well count myself among the top 1 billion software architects on the planet if I just went off and coded my component as pages and pages of formless Perl/Europa. No, no, no. I must first make class hierarchy diagrams, invent some directory structure guidelines, and worry about names of API methods. That's the key to success in this business.

Side-note/tangent/rant: there is an alternate Verilog style for coding combinational logic which would prefer the following for the tmp assignment:

  reg tmp;
  always @(a or b)
    tmp = a | b;

I think most programmers would report a long list of flaws in this style. For myself, I find that:

  • It doesn't do what it says: tmp is declared as a "reg", but is purely combinational
  • It's redundant: inputs to the expression must be declared in the "sensitivity list" (a or b), and appear again in the actual assignment (tmp = a | b)
  • It's too big: the superfluous 'always' block consumes more screen area, and requires more typing
  • It reveres historical baggage: Verilog began life as a simulation language; the construct above appears to be informed by that history, to the detriment of the goal at hand (to concisely define digital logic on a programmable chip)

That said, I admit (to my astonishment) that the above is a preferred coding style in the industry. Not a problem: in the end, the precise style of Verilog coding is irrelevant, because (in my so-humble opinion), if you're coding in Verilog, you've already made the wrong choice. So let's not fight this fight: we can leave Verilog style issues to the language lawyers, the guardians of legacy code bases, and those evil-doers with a vested interest in seeing that HDL coding remains a black art.


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Comments (2)

"If you're coding in Verilog, you've already made the wrong choice..." One could claim that there are worse choices than picking some well-supported industry standard language.

Meanwhile, googling for "verilog style" stuff, I find neutral-to-anti always-block-based combinational logic. That's just the web-writing portion of the industry of course.

opposed, with details of the pitfalls: http://www.csl.cornell.edu/courses/ece475/verilog.html

neutral, but interesting: http://www.neng.usu.edu/classes/ece/5460/notes/verilog_style_manual.pdf

Aaron Ferrucci:

...worse choices than picking some well-supported industry...

Aw, if you're going to be reasonable, how can I have any fun?

...neutral-to-anti always-block-based combinational logic...

I am shocked, sir, shocked. If this is correct, it means that a document I read on the Altera-internal twiki overstated its case!

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